PCB design guidelines for ESD suppression

PCB layout is a key element of ESD protection, rational PCB design can reduce the failure inspection and rework caused by unnecessary costs. In the PCB design, the use of transient voltage suppression device (TVS) diodes to suppress ESD discharge due to the direct charge injection, so the more important PCB design is to overcome the discharge current generated by electromagnetic interference (EMI) effects of electromagnetic fields.
Circuit loop
Current into the circuit by sensing loop, the loop is closed, and has a changing magnetic flux. Current amplitude is proportional to the area of ​​the ring. Larger loop contains more magnetic flux induced in the circuit and thus the strong current. Therefore, we must reduce the loop area.
The most common loop formed by the power supply and ground. Where possible conditions, can be used with a power and ground layers Multilayer PCB design. Multi-layer circuit board not only between the power and ground to minimize the loop area, but also reduces the high frequency EMI ESD pulses generated by the electromagnetic field.
If you can not use multi-layer circuit board, the power and ground for the wire must be connected to the grid shown in Figure 2. Grid connection can play the role of power and ground layers, each layer vias connecting traces, vias in each direction should be connected interval within 6 cm. In addition, the wiring, the power and ground traces as close as it can reduce the loop area.
Induction loop area and reduce
Another way to reduce the flow between the devices interconnected in parallel pathways. Must be longer than 30 cm when the signal cable, you can use Paul
Care line, a better way is placed near the signal line formations. Signal lines should protect the wire or the ground wire from the layer 13 mm or less, the length of each of the sensing element signal line (> 30 cm) or the power cord with ground lines are arranged to cross. The connection must cross from top to bottom or left to right are arranged at regular intervals.

Circuit connection length
Long signal lines can also become ESD pulse energy receiving antenna, try using a shorter signal line can reduce the signal line ESD electromagnetic field as a receiving antenna efficiency. Try to interconnect devices in adjacent positions, in order to reduce interconnection trace lengths. To charge injection
ESD on the ground floor of the direct discharge can damage sensitive circuitry. TVS diodes in use, while also using one or more high-frequency bypass capacitors, these capacitors are placed in vulnerable components of the power supply and ground. Bypass capacitor reduces the charge injection, maintaining the power and the voltage difference between the ground port. lcd module TVS that the sensed current shunt, keeping TVS clamp voltage potential difference. TVS and capacitor should be placed away from the protected IC as close as possible to ensure TVS path to ground, Low Temperature Display and a capacitor pin length is the shortest, to minimize parasitic inductance effects.
Connector must be mounted on the PCB copper platinum layer. Ideally, copper platinum layer PCB ground plane must be isolated from the pad connected via short.
Other PCB design guidelines
1 to avoid the edge of the PCB important signal line arrangements, such as a clock and reset signals;
2 on the PCB is set to the unused part of the ground;
3 chassis ground and signal line intervals of at least 4 mm;
4 maintain the aspect ratio of less than 5:1 chassis ground to minimize inductance effects;
5 with TVS diodes to protect all external connections;